1. Field of the Invention
The present invention relates to a power consumption analyzing apparatus and a power consumption analyzing method that analyze a power consumption of a semiconductor integrated circuit on a design stage.
2. Related Art
When designing a digital circuit composed of a flip-flop and a combinational logic circuit, it is general to use an RTL (Register Transfer Level) to describe the circuit. The circuit described by the RTL is converted into a gate-level netlist including connection information of the circuits by using logic synthesis. The netlist is laid out on a semiconductor substrate.
The netlist generated by the logic synthesis of the RTL description is not necessarily one type, and a plurality of types of net lists can be generated from the same RTL description. Although the netlist includes various kinds of circuits such as a flip-flop or a clock gating cell, a power consumption of the flip-flop is considerably larger than those of other cells, and hence the power consumption of the flip-flop must be accurately estimated.
The power consumption of the flip-flop is calculated from toggle rates and duty ratios of a data input signal, a clock signal, and a data output signal. Among others, toggle rates of the clock signal and the data output signal have a great influence on the power consumption. Therefore, to accurately estimate the power consumption of the flip-flop, the toggle rates of the clock signal and the data output signal must be accurately obtained.
The flip-flop (a register) included in RTL data written by using the RTL description is also present in the netlist. The toggle rate and the duty ratio of the data output signal of the flip-flop included in both of the RTL data and net list can obtain the same results, even if an operational simulation is executed based on either of the RTL data or the netlist.
On the other hand, the power consumption varies depending on whether the clock signal from the flip-flop has passed through the clock gating cell before being input to the flip-flop. Even if the clock gating cell is present in the netlist, there is a possibility that it is not present in the RTL data. In such a case, an operation of the clock gating cell cannot be verified even if the RTL is used to perform the operational simulation.
Under the circumstances, there is a problem that the power consumption of the clock-gated flip-flop cannot be accurately estimated even though an RTL simulation is performed. This problem may possibly occur in not only the flip-flop but also in all cells to which the clock signal is input.
There has been proposed a technology of analyzing a power consumption based on a result of executing an operational simulation using RTL data obtained by associating the RTL data with a gate-level netlist (see Japanese Patent Application Laid-open Publication No. 2006-190149).
However, in the above publication, the operational simulation is executed while ignoring a clock gating cell that is not present in RTL data but present in a gate-level netlist. Therefore, according to the technique of the above publication, it is difficult to accurately analyze power consumption.